69 lines
3.0 KiB
C
69 lines
3.0 KiB
C
/*
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* Copyright (c) 2014-2016 IBM Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "hw.h"
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//////////////////////////////////////////////////////////////////////
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// SPI 2
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//////////////////////////////////////////////////////////////////////
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// // NSS: PB12
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#define SCK_PORT 1 // SCK: PB13
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#define SCK_PIN 13
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#define MISO_PORT 1 // MISO: PB14
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#define MISO_PIN 14
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#define MOSI_PORT 1 // MOSI: PB15
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#define MOSI_PIN 15
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#define GPIO_AF_SPI2 0x05
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void spi_init (u1_t mode) {
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// enable clocks
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // GPIO ports B
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RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; // SPI interface 2
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// reset/stop
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SPI2->CR1 = 0; // clear SPE
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// use alternate function SPI2 (SCK, MISO, MOSI)
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hw_cfg_pin(GPIOx(SCK_PORT), SCK_PIN, GPIOCFG_MODE_ALT | GPIOCFG_OSPEED_40MHz | GPIO_AF_SPI2 | GPIOCFG_OTYPE_PUPD | GPIOCFG_PUPD_PDN);
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hw_cfg_pin(GPIOx(MISO_PORT), MISO_PIN, GPIOCFG_MODE_ALT | GPIOCFG_OSPEED_40MHz | GPIO_AF_SPI2 | GPIOCFG_OTYPE_PUPD | GPIOCFG_PUPD_PDN);
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hw_cfg_pin(GPIOx(MOSI_PORT), MOSI_PIN, GPIOCFG_MODE_ALT | GPIOCFG_OSPEED_40MHz | GPIO_AF_SPI2 | GPIOCFG_OTYPE_PUPD | GPIOCFG_PUPD_PDN);
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// configure and activate the SPI (master, internal slave select, software slave mgmt)
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// (use default mode: 8-bit, 2-wire, no crc, MSBF, PCLK/2, CPOL0, CPHA0)
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SPI2->CR1 = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM | SPI_CR1_SPE | (mode & 0x03);
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}
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// perform SPI transaction
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u1_t spi_xfer (u1_t out) {
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SPI2->DR = out;
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while( (SPI2->SR & SPI_SR_RXNE ) == 0);
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return SPI2->DR; // in
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}
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