77 lines
3.9 KiB
C
77 lines
3.9 KiB
C
/*
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* Copyright (c) 2014-2016 IBM Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "hw.h"
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#define GPIO_AF_BITS 4 // width of bit field
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#define GPIO_AF_MASK 0x0F // mask in AFR[0/1]
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#define GPIO_AFRLR(i) ((i)>>3)
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#define GPIO_AF_PINi(i,af) ((af)<<(((i)&7)*GPIO_AF_BITS))
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#define GPIO_AF_set(gpio,i,af) ((gpio)->AFR[GPIO_AFRLR(i)] = \
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((gpio)->AFR[GPIO_AFRLR(i)] \
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& ~GPIO_AF_PINi(i,GPIO_AF_MASK)) \
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| GPIO_AF_PINi(i,af))
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void hw_cfg_pin (GPIO_TypeDef* gpioport, u1_t pin, u2_t gpiocfg) {
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u1_t pin2 = 2*pin;
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GPIO_AF_set(gpioport, pin, gpiocfg & GPIOCFG_AF_MASK);
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gpioport->MODER = (gpioport->MODER & ~(3 << pin2)) | (((gpiocfg >> GPIOCFG_MODE_SHIFT ) & 3) << pin2);
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gpioport->OSPEEDR = (gpioport->OSPEEDR & ~(3 << pin2)) | (((gpiocfg >> GPIOCFG_OSPEED_SHIFT) & 3) << pin2);
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gpioport->OTYPER = (gpioport->OTYPER & ~(1 << pin )) | (((gpiocfg >> GPIOCFG_OTYPE_SHIFT ) & 1) << pin );
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gpioport->PUPDR = (gpioport->PUPDR & ~(3 << pin2)) | (((gpiocfg >> GPIOCFG_PUPD_SHIFT ) & 3) << pin2);
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}
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void hw_set_pin (GPIO_TypeDef* gpioport, u1_t pin, u1_t state) {
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gpioport->ODR = (gpioport->ODR & ~(1 << pin)) | ((state & 1) << pin );
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}
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void hw_cfg_extirq (u1_t portidx, u1_t pin, u1_t irqcfg) {
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // make sure module is on
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// configure external interrupt (every irq line 0-15 can be configured with a 4-bit port index A-G)
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u4_t tmp1 = (pin & 0x3) << 2;
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u4_t tmp2 = ((u4_t)0x0F) << tmp1;
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SYSCFG->EXTICR[pin >> 2] = (SYSCFG->EXTICR[pin >> 2] & ~tmp2) | (((u4_t)portidx) << tmp1);
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// configure trigger and enable irq
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u4_t mask = (u4_t)(1 << pin);
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EXTI->RTSR &= ~mask; // clear trigger
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EXTI->FTSR &= ~mask; // clear trigger
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switch(irqcfg & GPIO_IRQ_MASK) {
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case GPIO_IRQ_RISING: EXTI->RTSR |= mask; break; // trigger at rising edge
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case GPIO_IRQ_FALLING: EXTI->FTSR |= mask; break; // trigger at falling edge
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case GPIO_IRQ_CHANGE: EXTI->RTSR |= mask; EXTI->FTSR |= mask; break; // trigger at both edges
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}
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EXTI->IMR |= mask; // enable IRQ (pin x for configured port)
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// configure the NVIC
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u1_t channel = (pin < 5) ? (EXTI0_IRQn+pin) : ((pin<10) ? EXTI9_5_IRQn : EXTI15_10_IRQn);
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NVIC->IP[channel] = 0x70; // interrupt priority
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NVIC->ISER[channel>>5] = 1<<(channel&0x1F); // set enable IRQ
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}
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