396 lines
14 KiB
C
396 lines
14 KiB
C
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/**
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******************************************************************************
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* @file system_stm32l1xx.c
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* @author MCD Application Team
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* @version V1.2.0
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* @date 16-December-2014
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32L1xx Ultra
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* Low power devices, and is generated by the clock configuration
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* tool STM32L1xx_Clock_Configuration_V1.2.0.xls
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32l1xx_xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
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* function will do nothing and MSI still used as system clock source. User can
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* add some code to deal with this issue inside the SetSysClock() function.
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*
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* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
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* in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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* System Clock Configuration
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*=============================================================================
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* System Clock source | PLL(HSI)
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*-----------------------------------------------------------------------------
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* SYSCLK | 32000000 Hz
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*-----------------------------------------------------------------------------
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* HCLK | 32000000 Hz
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSE Frequency | 8000000 Hz
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*-----------------------------------------------------------------------------
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* PLL DIV | 3
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*-----------------------------------------------------------------------------
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* PLL MUL | 6
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*-----------------------------------------------------------------------------
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* VDD | 3.3 V
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*-----------------------------------------------------------------------------
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* Vcore | 1.8 V (Range 1)
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*-----------------------------------------------------------------------------
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* Flash Latency | 1 WS
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB clock | Disabled
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*-----------------------------------------------------------------------------
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*=============================================================================
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l1xx_system
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* @{
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*/
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/** @addtogroup STM32L1xx_System_Private_Includes
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* @{
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*/
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#include "stm32l1xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Variables
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* @{
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*/
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uint32_t SystemCoreClock = 32000000;
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__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/*!< Set MSION bit */
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RCC->CR |= (uint32_t)0x00000100;
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/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
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RCC->CFGR &= (uint32_t)0x88FFC00C;
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/*!< Reset HSION, HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xEEFEFFFE;
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/*!< Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
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RCC->CFGR &= (uint32_t)0xFF02FFFF;
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/*!< Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
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SetSysClock();
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Update SystemCoreClock according to Clock Register Values
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
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* value as defined by the MSI range.
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* MSI used as system clock */
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msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
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SystemCoreClock = (32768 * (1 << (msirange + 1)));
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break;
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case 0x04: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
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plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
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pllmul = PLLMulTable[(pllmul >> 18)];
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plldiv = (plldiv >> 22) + 1;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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if (pllsource == 0x00)
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{
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/* HSI oscillator clock selected as PLL clock entry */
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SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
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}
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else
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{
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/* HSE selected as PLL clock entry */
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SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
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}
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break;
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default: /* MSI used as system clock */
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msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
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SystemCoreClock = (32768 * (1 << (msirange + 1)));
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
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* settings.
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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/* Enable HSI */
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RCC->CR |= ((uint32_t)RCC_CR_HSION);
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/* Wait till HSI is ready and if Time out is reached exit */
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do
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{
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HSIStatus = RCC->CR & RCC_CR_HSIRDY;
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} while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
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{
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HSIStatus = (uint32_t)0x01;
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}
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else
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{
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HSIStatus = (uint32_t)0x00;
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}
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if (HSIStatus == (uint32_t)0x01)
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{
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/* Enable 64-bit access */
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FLASH->ACR |= FLASH_ACR_ACC64;
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTEN;
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/* Flash 1 wait state */
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FLASH->ACR |= FLASH_ACR_LATENCY;
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/* Power enable */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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/* Select the Voltage Range 1 (1.8 V) */
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PWR->CR = PWR_CR_VOS_0;
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/* Wait Until the Voltage Regulator is ready */
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while((PWR->CSR & PWR_CSR_VOSF) != RESET)
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{
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}
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/* HCLK = SYSCLK /1*/
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK /1*/
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK /1*/
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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/* PLL configuration */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
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RCC_CFGR_PLLDIV));
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL6 | RCC_CFGR_PLLDIV3);
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
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{
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}
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}
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else
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{
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/* If HSI fails to start-up, the application will have wrong clock
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configuration. User can add here some code to deal with this error */
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/
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