101 lines
3.7 KiB
C
101 lines
3.7 KiB
C
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/*
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* Copyright (c) 2014-2016 IBM Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "hw.h"
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#include "modem.h"
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// USART1
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#define USART USART1
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#define USART_TX_PORT GPIOA
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#define USART_TX_PIN 9
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#define USART_RX_PORT GPIOA
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#define USART_RX_PIN 10
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#define USART_AF 0x07
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#define USART_RCCREG APB2ENR
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#define USART_RCCVAL RCC_APB2ENR_USART1EN
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#define USART_IRQN USART1_IRQn
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#define USART_IRQHANDLER USART1_IRQHandler
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void usart_init () {
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hal_disableIRQs();
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// configure USART (115200/8N1)
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RCC->USART_RCCREG |= USART_RCCVAL;
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hw_cfg_pin(USART_TX_PORT, USART_TX_PIN, GPIOCFG_MODE_ALT|GPIOCFG_OSPEED_40MHz|GPIOCFG_OTYPE_PUPD|GPIOCFG_PUPD_PUP|USART_AF);
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hw_cfg_pin(USART_RX_PORT, USART_RX_PIN, GPIOCFG_MODE_ALT|GPIOCFG_OSPEED_40MHz|GPIOCFG_OTYPE_PUPD|GPIOCFG_PUPD_PUP|USART_AF);
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USART->BRR = 277; // 115200
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// configure NVIC
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NVIC->IP[USART_IRQN] = 0x70; // interrupt priority
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NVIC->ISER[USART_IRQN>>5] = 1 << (USART_IRQN&0x1F); // set enable IRQ
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// enable usart
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USART->CR1 = USART_CR1_UE;
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hal_enableIRQs();
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}
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void usart_starttx () {
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USART->CR1 |= (USART_CR1_TE | USART_CR1_TXEIE);
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}
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void usart_startrx () {
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USART->CR1 |= (USART_CR1_RE | USART_CR1_RXNEIE);
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}
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void USART_IRQHANDLER (void) {
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hal_disableIRQs();
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// check status reg (clears most of the flags)
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u4_t sr = USART->SR;
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if (sr & (USART_SR_PE|USART_SR_ORE|USART_SR_FE)) {
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hal_failed();
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}
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// check for tx reg empty
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if( (USART->CR1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE) ) {
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u2_t c = frame_tx(1);
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if((c & 0xFF00) == 0) { // send next char
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USART->DR = c;
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} else { // no more chars - wait for completion
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USART->CR1 &= ~USART_CR1_TXEIE;
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USART->CR1 |= USART_CR1_TCIE;
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}
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}
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// check for tx complete
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if( (USART->CR1 & USART_CR1_TCIE) && (sr & USART_SR_TC) ) {
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USART->CR1 &= ~(USART_CR1_TE | USART_CR1_TCIE); // stop transmitter
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frame_tx(0);
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}
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// check for rx reg not empty
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if( (USART->CR1 & USART_CR1_RXNEIE) && (sr & USART_SR_RXNE) ) {
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if(frame_rx(USART->DR) == 0) {
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USART->CR1 &= ~(USART_CR1_RE | USART_CR1_RXNEIE); // stop receiver
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}
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}
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hal_enableIRQs();
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}
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